تحقیق به زبان انگلیسی: A Study on Self-Timed Adders

تحقیق به زبان انگلیسی: A Study on Self-Timed Adders

عنوان تحقیق به زبان انگلیسی:

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A Study on Self-Timed Adders

شامل یک تحقیق جامع به زبان انگلیسی و با کمک نرم افزار latex به فرمت مقاله در اورده شده. که خلاصه ی جامعی از مقالات مرجع میباشد



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Design and Test Workshop, pp. 129-134, 2008



سفارش پروژه
موضوعات مرتبط: پروژه درسی، تحقیق به زبان انگلیسی
برچسب ها: A Study on Self, Timed Adders, تحقیق, تحقیق به زبان انگلیسی, latex
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تحقیق به زبان انگلیسی: Square Root And Squaring Algorithms

عنوان تحقیق به زبان انگلیسی:

Square Root And Squaring Algorithms

شامل یک تحقیق جامع به زبان انگلیسی و با کمک نرم افزار latex به فرمت مقاله در اورده شده. که خلاصه ی جامعی از مقالات مرجع میباشد



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properties of iterative square-rooting methods using high-speed multiplication,

” IEEE, vol. 21, Aug. 1972.

[2] B. F.Dinechin, M.Joldes and G.Revy,“ Multiplicative square root algorithms

for fpgas, IEEE, 2010.

[3] D. Zuras,“ More on Squaring and Multiplying Large Integers,” IEEE

Transactions on Computers, Vol. 43, No. 8, pp. 899-908, August 1994.

[4] J. Guajardo and C. Paar,“ Modified Squaring Algorithm,” Available from

http://www.crypto.ruhr-uni-bochum.de/guajard o/cv.htmlpubs.

[5] B. Parhami, “Computer Arithmetic-Algorithms and Hardware” Oxford



University Press, 2000.

low-power full-adder cell with new technique in desining logical gate based on static



مقاله شبیه سازی شده



کد پروژه:1531

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موضوع:گیت های منطقی Microelectronics



شبیه سازی مقاله به کمک hspice و L-editهمراه با Word و پاورپوینت





شامل:مقاله اصلی + فایل شبیه سازی با نرم افزارhspice +گزارش کامل از خلاصه ای از مقاله و نتایج شبیه سازی






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عنوان مقاله:

A novel low-power full-adder cell with new technique in desining logical gate based on static cmos inverter
سلول جمع کننده کم مصرف با تکنیکی جدید در طراحی گیت های منطقی

Address: sciencedirect
Abstract

A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18 μm and 90 nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.

Keywords

Low-power Full-adder; Low-power CMOS design; Inverter-based full-adder design; Transmission gate

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0936-729-2276
azsoft.ir
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azsoft.ir